1. Technical Field
The disclosure relates to a circuit and a method for correcting a duty cycle, and more particularly, to a circuit and a method for correcting a duty cycle, which can precisely correct the duty cycle of a clock signal.
2. Related Art
In general, in a semiconductor integrated circuit such as a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), data is processed by using both the rising edge and the falling edge of a clock signal to increase an operation speed. Therefore, if the ratio between the high level pulse width and the low level pulse width of a clock signal, that is, a duty ratio does not correspond to 50:50, operation efficiency is lowered. However, in substance, the clock signal generally employed in a semiconductor integrated circuit makes it difficult to have a precise duty ratio due to various factors related to how the semiconductor integrated circuit is mounted, such as noise, etc. Thus, in order to improve operation efficiency, the semiconductor integrated circuit is provided with a duty cycle correction circuit for correcting the duty ratio of a clock signal.
However, conventional duty cycle correction circuits, such as digital converter types and phase mixer types, suffer in their ability to correct the duty cycle and in that conventional duty cycle correction circuits have a large amount of power consumption, which is not sufficient to support the high performance operation of semiconductor integrated circuits.